Array sockets are widely used to seat a microchip on a circuit board so that the microchip may be replaced or upgraded to improve performance at a later date. Typical microchips include, but are not limited to, memory modules, microprocessors, and BIOS chips.
FIG. 1 is a cross-sectional view of an exemplary array socket system 100 including a microchip 120 having microchip pins 125 seated in corresponding pin receptacles (not shown) of an array socket 110. Array socket 110 includes a plurality of socket pins 145 that are electrically coupled within array socket 110 to the corresponding pin receptacles. Socket pins 145 are electrically connected to conductor traces 230 (FIG. 2) such that signals and/or power may be delivered to/from microchip 120 from other components on circuit board 140.
FIG. 2 is a view of a bottom side of circuit board 140 illustrating a plurality of pads 210, which electrically couple to corresponding socket pins 145. Conductor traces 230 form electrical contact with corresponding pads 210 and run outwards from pads 210 to various other electronic components mounted on or coupled to circuit board 140. Conductor traces 230 making contact with inner pads 210 must run between outer pads 210. As can be seen from FIG. 2, routing conductor traces 230 away from pads 210 can consume a large area on circuit board 140. As the number of microchip pins 120 increases, the number of pads 210 and conductor traces 230 increases. Thus, in complex microchips, finding a workable routing scheme becomes a complex task.
Furthermore, as microchips become faster, more powerful, and generally speaking more complicated, they demand increasing amounts of power and I/O paths. One solution has been to increase the number of microchip pins 120 to service the increasing number of I/O paths. Generally speaking, as the number of microchip pins 125 increases, the package I/O pitch P (FIGS. 3 and 4) between neighboring microchip pins 125 has continued to shrink to accommodate the added microchip pins 120 and corresponding conductor traces 230.
FIG. 3 illustrates a cross-sectional view taken at line A-A′ in FIG. 2, and FIG. 4 is an expanded view of an area B in FIG. 2. Vias 310 are created in circuit board 140 to allow socket pins 145 to pass through to the under side of circuit board 140. In a four-layer circuit board, there typically is a ground conductor layer 320A and a power conductor layer 320B. When via 310 is created in circuit board 140, an anti-pad 410 is created by etching back the copper of ground conductor layer 320A and power conductor layer 320B. Anti-pad 410 ensures that a short circuit does not occur between pad 210 and either one of ground conductor layer 320A or power conductor layer 320B. Consequently, conductor traces 230 are limited in width W by the distance between neighboring anti-pads 410.
Thus, as the trend continues towards tighter package I/O pitches P, width W of conductor traces 230 servicing pads 210 must also shrink. Currently, width W is 1.27 mm, but designs are in the works for package I/O pitches P ranging from 1 mm to as low as 0.4 mm. A step down to a package I/O pitch P of 1 mm results in a loss of approximately 21% in width W. As width W decreases the copper to delivery power to microchip 120 decreases. Reduced width W of conductor traces 230 results in a higher linear resistance and increased power loss and heat dissipation in conductor traces 230. The current trend of tighter I/O package pitches P is cornering chip designers into a two-fold problem-reduced power delivery capacity and increased power supply demand.